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vishay siliconix dg406, dg407 document number: 70061 s11-0179-rev. j, 07-feb-11 www.vishay.com 1 16-ch/dual 8-ch high-performance cmos analog multiplexers features ? low on-resistance - r ds(on) : 50 ? ? low charge injection - q: 15 pc ? fast transition time - t trans : 200 ns ? low power: 0.2 mw ? single supply capability ? 44 v supply max. rating benefits ? higher accuracy ? reduced glitching ? improved data throughput ? reduced power consumption ? increased ruggedness ? wide supply ranges: 5 v to 20 v applications ? data acquisition systems ? audio signal routing ? medical instrumentation ? ate systems ? battery powered systems ? high-rel systems ? single supply systems description the dg406 is a 16 channel single-ended analog multiplexer designed to connect one of sixteen inputs to a common output as determined by a 4-bit binary address. the dg407 selects one of eight differential inputs to a common differential output. break-before-make switching action protects against moment ary shorting of inputs. an on channel conducts current equally well in both directions. in the off state each channel blocks voltages up to the power supply rails. an enable (en) function allows the user to reset the multiplexer/dem ultiplexer to all switches off for stacking several devices. all control inputs, address (a x ) and enable (en) are ttl compatible over the full specified operating temperature range. applications for the dg406, dg407 include high speed data acquisition, audio signal switching and routing, ate systems, and avionics. high performance and low power dissipation make them ideal for battery operated and remote instrumentation applications. designed in the 44 v silicon-gate cmos process, the absolute maximum voltage rating is extended to 44 v, allowing operation with 20 v supplies. additionally single (12 v) supply operation is allowed. an epitaxial layer prevents latchup. for applications information please request documents 70601 and 70604. functional block diagram and pin configuration * pb containing terminations are not rohs compliant, exemptions may apply v+ s 11 s 10 s 9 nc a 3 d s 2 s 1 gnd a 1 a 2 nc dual-in-line and soic wide-body a 0 en v- nc s 8 s 16 s 7 s 15 s 6 s 14 s 5 s 13 s 4 s 12 s 3 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 top view 920 10 19 11 12 18 17 13 16 14 15 dg406 decoders/drivers dg407 v+ s 3b s 2b s 1b nc nc d a s 2a s 1a gnd a 1 a 2 d b dual-in-line and soic wide-body a 0 en v- nc s 8a s 8b s 7a s 7b s 6a s 6b s 5a s 5b s 4a s 4b s 3a 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 top view 9220 10 19 11 12 18 17 13 16 14 15 decoders/drivers a v aila b le p b -free rohs* compliant
www.vishay.com 2 document number: 70061 s11-0179-rev. j, 07-feb-11 vishay siliconix dg406, dg407 functional block diagram and pin configuration logic ?0? = v al ?? 0.8 v logic ?1? = v ah ?? 2.4 v x = do not care decoders/drivers 7 8 9 5 20 19 21 22 23 24 25 1 2 3 4 10 11 12 13 14 15 16 17 18 26 27 28 top view 6 plcc and lcc s 13 s 15 s 5 s 12 s 4 s 7 s 11 s 14 s 6 s 3 s 10 s 2 s 9 s 1 s gnd nc nc nc 3 v+ 2 d 1 v- 0 s en dg406 a a a a 16 8 s 7b s 5a s 4b s 4a s 7a s 3b s 6b s 6a s 3a s 5b s 2b s 2a s 1b s 1a plcc and lcc top view gnd nc nc d nc v+ d v- en s 2 1 0 s a a a 8b 8a b a dg407 decoders/drivers 7 8 9 5 20 19 21 22 23 24 25 1 2 3 4 10 11 12 13 14 15 16 17 18 26 27 28 6 truth table (dg406) a 3 a 2 a 1 a 0 en on switch x x x x 0 none 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16 truth table (dg407) a 2 a 1 a 0 en on switch pair x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 ordering information (dg406) temp. range package part number - 40 c to 85 c 28-pin plastic dip dg406dj dg406dj-e3 28-pin plcc dg406dn DG406DN-T1-E3 28-pin widebody soic dg406dw dg406dw-e3 ordering information (dg407) temp. range package part number - 40 c to 85 c 28-pin plastic dip dg407dj dg407dj-e3 28-pin plcc dg407dn dg407dn-t1-e3 28-pin widebody soic dg407dw dg407dw-e3
document number: 70061 s11-0179-rev. j, 07-feb-11 www.vishay.com 3 vishay siliconix dg406, dg407 notes: a. signals on sx, dx or inx exceeding v+ or v- will be clamped by internal diodes. limit forward diode current to maximum curre nt ratings. b. all leads soldered or welded to pc board. c. derate 6 mw/c above 75c. d. derate 12 mw/c above 75c. e. derate 13.5 mw/c above 75c . absolute maximum ratings parameter limit unit voltages referenced to v- v+ 44 v gnd 25 digital inputs a , v s , v d (v-) - 2 to (v+) + 2 v or 20 ma, whichever occurs first current (any terminal) 30 ma peak current, s or d (pulsed at 1 ms, 10 % duty cycle max.) 100 storage temperature (ak, az suffix) - 65 to 150 c (dj, dn suffix) - 65 to 125 power dissipation (package) b 28-pin plastic dip b 625 mw 28-pin cerdip d 1.2 w 28-pin plastic plcc c 450 mw lcc-28 e 1.35 w 28-pin widebody soic 450 mw
www.vishay.com 4 document number: 70061 s11-0179-rev. j, 07-feb-11 vishay siliconix dg406, dg407 specifications a parameter symbol test conditions unless otherwise specified v+ = 15 v, v- = - 15 v v al = 0.8 v, v ah = 2.4 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full - 15 15 - 15 15 v drain-source on-resistance r ds(on) v d = 10 v, i s = - 10 ma sequence each switch on room full 50 100 125 100 125 ? r ds(on) matching between channels g ? r ds(on) v d = 10 v room 5 % source off leakage current i s(off) v en = 0 v v d = 10 v v s = 10 v room full 0.01 - 0.5 - 50 0.5 50 - 0.5 - 5 0.5 5 na drain off leakage current i d(off) dg406 room full 0.04 - 1 - 200 1 200 - 1 - 40 1 40 dg407 room full 0.04 - 1 - 100 1 100 - 1 - 20 1 20 drain on leakage current i d(on) v s = v d = 10 sequence each switch on dg406 room full 0.04 - 1 - 200 1 200 - 1 - 40 1 40 dg407 room full 0.04 - 1 - 100 1 100 - 1 - 20 1 20 digital control logic high input voltage v inh full 2.4 2.4 v logic low input voltage v inl full 0.8 0.8 logic high input current i ah v a = 2.4 v, 15 v full - 1 1 - 1 1 a logic low input current i al v en = 0 v, 2.4 v, v a = 0 v full - 1 1 - 1 1 logic input capacitance c in f = 1 mhz room 7 pf dynamic characteristics transition time t trans see figure 2 room full 200 350 450 350 450 ns break-before-make interval t open see figure 4 room full 50 25 10 25 10 enable turn-on time t on(en) see figure 3 room full 150 200 400 200 400 enable turn-off time t off(en) room full 70 150 300 150 300 charge injection q v s = 0 v, c l = 1 nf, r s = 0 ? room 15 pc off isolation h oirr v en = 0 v, r l = 1 k ? f = 100 khz room - 69 db source off capacitance c s(off) v en = 0 v, v s = 0 v, f = 1 mhz room 8 pf drain off capacitance c d(off) v en = 0 v v d = 0 v f = 1 mhz room 130 dg407 room 65 drain on capacitance c d(on) dg406 room 140 dg407 room 70 power supplies positive supply current i+ v en = v a = 0 or 5 v room full 13 30 75 30 75 a negative supply current i- room full - 0.01 - 1 - 10 - 1 - 10 positive supply current i+ v en = 2.4 v, v a = 0 v room full 50 500 900 500 700 negative supply current i- room full - 0.01 - 20 - 20 - 20 - 20
document number: 70061 s11-0179-rev. j, 07-feb-11 www.vishay.com 5 vishay siliconix dg406, dg407 notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. e. guaranteed by design, no t subject to production test. f. v in = input voltage to perform proper function. g. ? r ds(on) = r ds(on) max. - r ds(on) min. h. worst case isolation occurs on channel 4 due to proximity to the drain pin. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications a (for single supply) parameter symbol test conditions unless otherwise specified v+ = 12 v, v- = 0 v v al = 0.8 v, v ah = 2.4 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 0 12 0 12 v drain-source on-resistance r ds(on) v d = 3 v, 10 v, i s = - 1 ma sequence each switch on room 90 120 120 ? r ds(on) matching between channels g ? r ds(on) room 5 % source off leakage current i s(off) v en = 0 v v d = 10 v or 0.5 v v s = 0.5 v or 10 v room 0.01 na drain off leakage current i d(off) dg406 room 0.04 dg407 room 0.04 drain on leakage current i d(on) v s = v d = 10 sequence each switch on dg406 room 0.04 dg407 room 0.04 dynamic characteristics switching time of multiplexer t open v s1 = 8 v, v s8 = 0 v, v in = 2.4 v room 300 450 450 ns enable turn-on time t on(en) v inh = 2.4 v, v inl = 0 v v s1 = 5 v room 250 600 600 enable turn-off time t off(en) room 150 300 300 charge injection q c l = 1 nf, v s = 6 v, r s = 0 room 20 pc power supplies positive supply current i+ v en = 0 v or 5 v, v a = 0 v or 5 v room full 13 30 75 30 75 a negative supply current i- room full - 0.01 - 20 - 20 - 20 - 20
www.vishay.com 6 document number: 70061 s11-0179-rev. j, 07-feb-11 vishay siliconix dg406, dg407 typical characteristics (t a = 25 c, unless otherwise noted) r ds(on) vs. v d and supply r ds(on) vs. v d and supply i d , i s leakages vs. temperature v d - drain voltage (v) 160 120 80 40 0 - 20 20 - 4 - 12 4 12 5 v 10 v 12 v 15 v 20 v 8 v - on-resistance ( ) r ds(on) v d - drain voltage (v) 160 120 80 40 0 020 4 8 12 16 v+ = 7.5 v 200 240 v- = 0 v 10 v 12 v 15 v 20 v 22 v - on-resistance ( ) r ds(on) temperature (c) - current , i s i d v+ = 15 v v- = - 15 v v d = "14 v i d(on) , i d(of f) i s( of f) 100 na 10 na 1 na 100 pa 10 pa 1 pa 0.1 pa - 55 - 35 - 15 5 2 5 4 5 6 5 8 5 105 125 r ds(on) vs. v d and temperature i d , i s leakage currents vs. analog voltage switching times vs. bipolar supplies v d - drain voltage (v) 0 40 30 20 10 80 70 60 50 15 10 5 - 15 - 10 - 5 0 - 55 c - 40 c 0 c 25 c 85 c 125 c v+ = 15 v v- = - 15 v - on-resistance ( ) r ds(on) v s , v d - source drain voltage (v) - current (pa) , i s i d 120 - 120 - 15 - 10 - 5 0 5 10 15 - 80 - 40 0 40 80 v+ = 15 v v- = - 15 v v s = - v d for i d(of f) v d = v s(open) for i d(on) dg406 i d(on) , i d(of f) i s( of f) dg407 i d(on) , i d(of f) v suppl y - supply voltage (v) time (ns) 350 300 150 100 50 0 5 10 15 20 200 250 t tra n s t on(e n) t off(e n )
document number: 70061 s11-0179-rev. j, 07-feb-11 www.vishay.com 7 vishay siliconix dg406, dg407 typical characteristics (t a = 25 c, unless otherwise noted) switching times vs. single supply off-isolation vs. frequency t on /t off vs. temperature v+ - supply voltage (v) t ime (ns) 700 600 300 200 100 0 51 0 1 5 20 400 500 t tra n s t on(e n) t off(e n ) v- = 0 v f - frequency (hz) isol (db) - 80 - 60 - 40 - 20 0 10k 100k 1m 10m - 100 - 120 1k 100 - 140 temperature (c) time (ns) 180 140 100 60 220 t on(e n) t off(e n ) t tra n s 260 300 v+ = 15 v v- = - 15 v - 55 - 35 125 - 15 5 25 45 65 85 105 charge injection vs. analog voltage supply currents vs. switching frequency switching threshold vs. supply voltage v s - source voltage (v) q (pc) 0 40 30 20 10 70 60 50 15 10 5 - 15 - 10 - 5 0 v+ = 15 v , v- = - 15 v v+ = 12 v , v- = 0 v f - frequency (hz) i - current (ma) 10 - 10 10 100 1k 10k 100k 1m 10m 0 4 6 i gnd 2 8 i- i+ e n = 5 v a x = 0 or 5 v - 8 - 6 - 4 - 2 v supply - supply voltage (v) (v) v th 3 1 0 510 15 20 2 0
www.vishay.com 8 document number: 70061 s11-0179-rev. j, 07-feb-11 vishay siliconix dg406, dg407 schematic diagram (typical channel) test circuits figure 1. en a 0 gnd s 1 v+ d v+ s n v- decode/ drive level shift v- v+ v ref a x figure 2. transition time logic input switch output v s8 v o t tra n s t r < 20 ns t f < 20 ns s 8 on s 1 on t tra n s 0 v v s1 50 % 90 % 90 % 3 v 0 v dg406 s 1b s 8b a 2 d b a 1 * a 0 * = s 1a - s 8a , s 2b s 7b , d a 50 300 v o 10 v 10 v + 2.4 v + 15 v - 15 v en v+ v- gnd 35 pf s 1 s 2 - s 15 s 16 a 2 a 1 a 0 50 300 v o a 3 10 v 10 v + 2.4 v + 15 v - 15 v en v+ v- gnd d 35 pf dg407
document number: 70061 s11-0179-rev. j, 07-feb-11 www.vishay.com 9 vishay siliconix dg406, dg407 test circuits figure 3. enable switching time v o t r < 20 ns t f < 20 ns v o logic input t on(en) 90 % switch output 50 % t off(en) 3 v 0 v 0 v a 1 50 a 0 s 1 v o a 2 - 5 v + 15 v - 15 v 300 en s 2 - s 16 v+ v- gnd d 35 pf a 3 v o s 1b a 2 s 1a - s 8a s 2b - s 8b a 1 d a and d b a 0 50 300 + 15 v - 15 v en v+ v- gnd 35 pf dg406 dg407 - 5 v 90 % figure 4. break-before-make interval 50 % 80 % logic input switch output v o v s t open t r < 20 ns t f < 20 ns 0 v 3 v 0 v 50 a 0 all s and d a 300 a 3 d,d b a 1 a 2 + 2.4 v + 15 v - 15 v en v+ v- v o gnd + 5 v 35 pf dg406 dg407
www.vishay.com 10 document number: 70061 s11-0179-rev. j, 07-feb-11 vishay siliconix dg406, dg407 applications hints sampling speed is limited by two consecutive events: the transition time of the multiplexe r, and the settling time of the sampled signal at the output. t trans is given on the data sheet. settling time at the load depends on several parameters: r ds(on) of the multiplexer, source impedance, multiplexer and load capacitances, charge injection of the multiplexer and accuracy desired. the settling time for the multiplexer alone can be derived from the model shown in figure 5. assuming a low impedance signal source like that presented by an op amp or a buffer amplifier, the settling time of the rc network for a given accuracy is equal to n ? : the maximum sampling frequency of the multiplexer is: (1) where n = number of channels to scan t settling = n ? = n x r ds(on) x c d(on) for the dg406 then, at room temp and for 12-bit accuracy, using the maximum limits: (2) or f s = 694 khz (3) from the sampling theorem, to properly recover the original signal, the sampling frequency should be more than twice the maximum component frequency of the original signal. this assumes perfect bandlimiting. in a real application sampling at three to four times the filter cutoff frequency is a good practice. therefore from equation 2 above: (4) from this we can see that the dg406 can be used to sample 16 different signals whose maximum component frequency can be as high as 173 khz. if for example, two channels are used to double sample the same incoming signal then its cutoff frequency can be doubled. the block diagram shown in figure 6 illustrates a typical data acquisition front end suitable for low-level analog signals. differential multiplexing of small signals is preferred since this method helps to reject any common mode noise. this is especially important when the sensors are located at a distance and it may eliminate the need for individual amplifiers. a low r ds(on) , low leakage multiplexer like the dg407 helps to reduce measurement errors. the low power dissipation of the dg407 minimizes on-chip thermal gradients which can cause errors due to temperature mismatch along the parasitic thermocouple paths. please refer to application note an203 for additional information. vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70061 . % accuracy # bits n 0.25 8 6 0.012 12 9 0.0017 15 11 figure 5. simplified model of one multiplexer channel r s = 0 r ds(on) v out c d(on) f s = 1 n (t settli n g + t tra n s ) f s = 1 16 (9 x 100 x 10 -12 f) + 300 x 10 -12 s f c = 1 4 x f s = 173 khz figure 6. measuring low-level analog signals is more accu rate when using a differential multiplexing technique 12-bit a/d converter analog multiplexer dg407 controller to sensor 1 to sensor 8 inst amp s/h
e 1 e q 1 a l a(1) e 1 b b 1 s c e a l a 1 d 15 max. 1234567891011121314 28 27 26 25 24 23 22 21 20 19 18 17 16 15 package information vishay siliconix document number: 71243 06-jul-01 www.vishay.com 1

dim min max min max 2.29 5.08 0.090 0.200 0.39 1.77 0.015 0.070 0.38 0.56 0.015 0.022 0.89 1.65 0.035 0.065 0.204 0.30 0.008 0.012 35.10 39.70 1.380 1.565
15.24 15.88 0.600 0.625
13.21 14.73 0.520 0.580 2.29 2.79 0.090 0.110 14.99 15.49 0.590 0.610 2.60 5.08 0.100 0.200 0.95 2.345 0.0375 0.0925 0.995 2.665 0.0375 0.105 ecn: s-03946?rev. f, 09-jul-01 dwg: 5488
document number: 71264 www.vishay.com 28-sep-09 1 package information vishay siliconix plcc: 28-lead d 0.101 mm 0.004" d-square d 1 -square b b 1 e 1 a 1 a a 2 d 2 dim. millimeters inches min. max. min. max. a 4.20 4.57 0.165 0.180 a 1 2.29 3.04 0.090 0.120 a 2 0.51 - 0.020 - b 0.331 0.553 0.013 0.021 b 1 0.661 0.812 0.026 0.032 d 12.32 12.57 0.485 0.495 d 1 11.430 11.582 0.450 0.456 d 2 9.91 10.92 0.390 0.430 e 1 1.27 bsc 0.050 bsc ecn: t09-0766-rev. d, 28-sep-09 dwg: 5491
package information www.vishay.com vishay siliconix revision: 01-aug-11 1 document number: 71268 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 soic (wide-body): 28-leads ecn: e11-2209-rev. d, 01-aug-11 dwg: 5850 0.3525 0.001 0.06 0.002d cavity no. 0.295 0.001 0.070 0.005 0.1475 0.001 0.055 0.005 pin 1 indicator 0.047 0.007 0.001 dp surface polished 0.010 0.334 0.005 r0.004 r0.008 r0.009 r0.004 0.032 0.005 4 2 0.041 0.001 0.705 0.001 0.091 0.001 0.017 0.0003 0.050 typ. 0.00825 0.00325 0.098 0.002 0.334 0.005 0.291 0.001 0.295 0.001 0.406 0.004 r0.004 7 (4 ) 0.020 45 detail a detail a 1 2345678 28 27 26 25 24 23 22 21 910 20 19 11 18 12 17 13 16 14 15 all dimensions in inches
d l 1 e b l e a 1 a 28 1 2 package information vishay siliconix document number: 71278 02-jul-01 www.vishay.com 1

dim min max min max 1.37 2.24 0.054 0.088 1.63 2.54 0.064 0.100 0.56 0.71 0.022 0.028 11.23 11.63 0.442 0.458 11.23 11.63 0.442 0.458 1.27 bsc 0.050 bsc 1.14 1.40 0.045 0.055 1.96 2.36 0.077 0.093 ecn: s-03946?rev. b, 09-jul-01 dwg: 5319
e 1 e q 1 a l a 1 e 1 b b 1 l 1 s c e a d 12 3 28 package information vishay siliconix document number: 71283 03-jul-01 www.vishay.com 1
dim min max min max a 4.06 5.92 0.160 0.232 a 1 0.38 1.52 0.015 0.060 b 0.38 0.51 0.015 0.020 b 1 1.14 1.65 0.045 0.065 c 0.20 0.30 0.008 0.012 d 36.58 37.08 1.440 1.460 e 15.24 15.88 0.600 0.625 e 1 12.95 13.46 0.510 0.530 e 1 2.54 bsc 0.100 bsc e a 15.24 bsc 0.600 bsc l 3.18 3.81 0.125 0.150 l 1 3.81 5.08 0.150 0.200 q 1 1.27 2.16 0.050 0.085 s 1.52 2.29 0.060 0.090 0 15 0 15 ecn: s-03946?rev. e, 09-jul-01 dwg: 5434
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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